The present invention relates generally to the fabrication of a semiconductor device and more particularly to a method of forming a graded junction comprising multiple doped regions in the semiconductor device.
During semiconductor fabrication, numerous doped regions are formed in a semiconductor substrate. These doped regions perform various functions, such as source and drain regions for metal-oxide-semiconductor (MOS) transistors, buried electrical signal lines, substrate resistors and the like. Often, it is necessary to form doped regions having varying junction depths in order to meet different electrical resistance requirements and current handling requirements of a semiconductor device. Because of the electrical field created by a buried junction, the geometric profile of the junction can be important where electric components having extremely small feature sizes are being fabricated. For example, a lightly-doped-drain (LDD) structure in a channel region of an MOS transistor is necessary to insure proper functioning of a sub-micron transistor. Additionally, in advanced electrically-erasable-programmable-read-only-memory (EEPROM) devices, pocket regions are fabricated in a semiconductor substrate having a precise junction profile within the substrate.
Product development efforts in EEPROM device technology have focused on increasing programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. EEPROM device designers have taken advantage of the ability of silicon nitride to store charge in localized regions and have designed memory circuits that utilize two regions of stored charge within an oxide-nitride-oxide (ONO) layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of approximately equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two bits to be programmed and read concurrently. The two bits of the memory cell can be erased individually by applying suitable erase voltages to the gate and to either the source or drain regions. The two-bit memory cell utilizes pocket regions adjacent to a buried bit-line region. Electrons are sourced from the pocket regions and injected into the silicon nitride layer.
As advanced MOS and EEPROM devices are scaled to smaller dimensions, it becomes more difficult to form the doped regions at precise locations in the substrate. In particular, the pocket regions of EEPROM arrays using two-bit data storage and the LDD regions of MOS transistors must be carefully fabricated to avoid excessive overlap with the source and drain regions. Accordingly, as device dimensions are scaled to smaller values, advances in fabrication technology are necessary to insure proper functioning devices. Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to a method of forming a graded junction in a semiconductor substrate. In particular, the method can be utilized in a formation of pocket regions in an EEPROM device by performing a step of doping the semiconductor substrate at an angle of incidence substantially normal to a surface of the semiconductor substrate.
According to one aspect of the present invention, a method of forming a graded junction is disclosed, wherein a first masking pattern is formed over a surface of a semiconductor substrate, wherein the first masking has a first opening associated therewith. The first opening is associated with a first region of the semiconductor substrate, and is characterized by a first lateral dimension. The semiconductor substrate is doped with a first dopant, wherein the first masking pattern is generally used as a doping mask, thereby doping the first region of the semiconductor substrate with a first conductivity associated with the first dopant.
According to another aspect of the present invention, the first masking pattern is swelled to decrease the first lateral dimension of the first opening. The swelled first masking pattern therefore defines a second lateral dimension of the first opening, wherein the second lateral dimension is smaller than the first lateral dimension. Furthermore, the swelled first masking pattern generally overlies one or more portions of the first dopant region. According to one exemplary aspect of the invention, a RELACS process is performed to swell the first masking pattern.
In accordance with yet another aspect of the present invention, the semiconductor substrate is doped with a second dopant, wherein the swelled first masking pattern is used as a doping mask. Doping the semiconductor substrate with the second dopant defines a second dopant region. Portions of the first dopant region, however, generally retain the characteristics and conductivity of the first dopant, thereby defining pocket regions in the semiconductor substrate adjacent to the second dopant region, and furthermore defining a graded junction within the semiconductor substrate.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.